AMC520
・Double width per μTCA.4
・Ten channel of ADC with 125MSPS @ 16-bit resolution utilizing AD9268 device
・Dual 1GbE via SFP
・Dual DAC with 250 MSPS @ 16-bit resolution utilizing MAX5878
・Internal clock or precision external clock from either RTM or back plane clocks
・Trig in/out configurable by software (external trigger via front, RTM or port 17)
・PCIe x4 or x8, GbE (FPGA programmable)
・Xilinx Virtex-6 FPGA in FF1759 package
・Option for QDR-II+
・AMC FCLKA, TCLKA, TCLKB, TCLKC and TCLKD are routed
・On board PLL for buffering/multiplying and jitter cleaner
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